The release of the CMOS low-power library by the Infopad group at UC Berkeley [1] gave engineers the ability to develop low power circuits under Magic using standard cells with minimum geometry layouts [2].

In this paper, we describe a process that translates this low-power standard cell library from Magic into Mentor Graphics format. Using the Design Kit Example (DKE), we build a cohesive library structure that allows low-power semicustom design, using schematic capture with Design Architect (DA) or synthesis with AutoLogic II, digital simulation with QuickSim II, and physical layout in IC Station. We describe the library structure in terms of the QuickPart modeling tables, layout conversion through the GDS II stream, and the development of the technology files. This new library will provide a low-power alternative to the presently available MDK. The initial targeted technology will be the HP 1.2 micron 2-metal process available through MOSIS.

Many timing models for ASIC layout assume that the supply voltage is in the 5 Volt range, with some linear voltage supply derating constant. In order to effectively use a low-power library, we modify the DKE equation examples to calculate delay times with voltage supplies anywhere between the 1 volt and 5 volt range [3]. We describe delay equations for the technology file that model the exponential increasing delay times in relation to the supply voltage, as well as the separation of the propagation delays and pin rise and fall times in the digital simulation. These models provide a metric of evaluating the supply voltage's impact on design performance.

Future work for this library will include power estimation techniques tied in with the digital modeling as a further metric to judge the effectiveness of low-power architecture techniques. Further work will also be needed for porting the library to submicron processes, which use an increased number of metal layers and slightly different lambda rules. Since we tried to automate the process as much as possible, the library translation method described in this paper can be also used with minimal effort for translating other libraries, like the one available from MSU [4].

This work is partially supported by NSF Career Grant MIP-9703440.

1. http://infopad.EECS.Berkeley.EDU/infopad-ftp/software/low_power_library/
2. http://www.research.digital.com/wrl/projects/magic/magic.html
3. Chandrakasan, A., Sheng, S., Broderson, R., Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits. Vol 27. No 4., April 1992.
4. http://www.erc.msstate.edu/mpl/libraries/stdcells/cell_info.html

Bio:
David C. Garrett is working on his doctoral degree in electrical engineering at the University of Virginia's Center for Semicustom Integrated Systems in Charlottesville, Virginia. His main research interest is in low-power VLSI design, with other interests in wireless communications system and neural networks. Before beginning his doctoral study, he was with Lockheed Martin Armament Systems in Burlington, Vermont. There he worked on circuit testing and automated test equipment designs, as well as embedded hardware and software design. Dave is a graduate of the Engineering Leadership Development Program at Lockheed Martin. While working at Lockheed Martin, he pursued a Masters Degree in electrical engineering part-time from the University of Vermont, graduating May 1997. Before working for Lockheed Martin, Dave graduated from the University of Virginia with Distinction in 1994 with a BSEE, and was a member of both Eta Kappa Nu Electrical Engineering Honor Society and Tau Beta Pi Engineering Honor Society. During his undergraduate work, he performed research as a NASA Langley Research Center Summer Scholar.

Mircea R. Stan has been an Assistant Professor in the Electrical Engineering Department at the University of Virginia since September 1996. His graduate degrees, MS and PhD in Computer Engineering, were awarded by the University of Massachusetts at Amherst in 1994 and 1996. His research interests are in low-power VLSI, analog and digital mixed-signal circuits, FPGAs for reconfigurable architectures and embedded systems. Prior to his graduate work, Mircea accumulated more than seven years of industrial experience as an R&D Engineer in Romania, Japan and the United States. In industry, he was involved in the design of intelligent peripheral device controllers and participated in the architecture definition of a minicomputer and in the design of a professional digital voice logger. Mircea is a member of the IEEE, ACM and Usenix professional societies. He is also a member of the Phi Kappa Phi and Sigma XI honor societies and has been recently awarded an NSF CAREER grant for developing low-power design methods and tools.