Rapid changes to design flows to accommodate deep submicron design issues require EDA vendors to focus more of their development tasks on algorithm invention. Standards for EDA enable this by assuring the reuse of library information and design information by multiple applications from multiple vendors. This paper presents an update on important current and emerging standards will be given.

Bio:
Dennis B. Brophy is standards program manager for Mentor Graphics' silicon vendor operations. Dennis has been in the electronic design automation industry for the past 17 years. He was first with Hewlett-Packard for five years, then joined Mentor Graphics where he has held several positions the past 12 years. Dennis is the chair of the IEEE P1481 Delay and Power Calculation Working Group and chair of the IEEE 1076.4 Timing Working Group Technical Action Group (VITAL TAG). He is currently leading a group to standardize a delay and power calculation system which includes EDA vendor independent calculation methods to ensure timing and power calculation coherency across a broad set of EDA applications. He is also leading a group to extend the VITAL 1995 standard to include a built-in memory model, more accurate interconnect delay model, built-in skew check, and improvements to VITAL timing checks. Dennis is a board member of Open Verilog International and a board member of Virtual Socket Interface (VSI) Alliance for Mentor Graph ics. He received a Bachelor of Science from the University of California at Davis in electrical engineering and computer engineering in 1980.