This paper presents a practical approach to building a library of FPGA targeted pipelined coprocessors, from modular and scalable VHDL behavioral descriptions. Considering that fully hardware/software system partioning is difficult, and that this problem lacks a definitive solution, the use of a library of reconfigurable coprocessors to resolve computational bottlenecks appears as a natural extension of the existing software signal processing libraries. As a typical example from a class of applications operating by way of a sliding window over a 2-D array, this paper describes the design of 3x3 convolution coprocessor for the TMS320C40DSP microprocessor. The trade-offs made to meet size and speed constraints reflect the importance of the designer's role in helping high-level synthesis tools produce efficient designs. The architecture of the 3x3 convolution coprocessor is shown to be of a general form that can be adapted to convolution kernels of any size.

Bio:
Guy Bois is assistant professor at Ecole Polytechnique of Montreal. He has worked for 10 years on various aspects of VLSI circuit synthesis. His interests include hardware/software codesign for digital signal processing and algorithms for VLSI physical design automation.