As interconnects occupy a major part of modern integrated circuits, reducing delays is becoming a main concern for designers. In particular delays due to clocking network is very critical for proper operation of the circuit. In addition to frequency synthesis, Phase locked- loops have been used extensively in clock recovery. As they become an integral part of microprocessors, interest is growing in the use of all digital phase locked-loops (ADDLL). Compared to their analog version, they have the following advantages: quicker to initialize, higher noise immunity, easier to test, no special passive devices, traditional CMOS process, shorter time to market.

In this paper we present the design, operation and performance of two stages adjusting ADPLL that restores the skew due to clock generator/buffer. The ADPLL recovers delay ranging within 4 and 40 Ns within 17 system clock periods. Mentor Graphics tools have been used at all stages of the design.

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