Memory devices are increasingly becoming an important aspect of ASIC designs.Increasing design complexities, force the need to model memory devices with a high level of accuracy and simulation efficiency. Library developers have long found it relatively easy to model memories in the Verilog HDL compared to VHDL.

VITAL Technical Action Group (TAG) hopes to change this notion with the proposed memory modeling extensions as part of VITAL 1076.4 ASIC Modeling standard. Currently being developed when these extensions become part of the updates planned for VITAL '98, the whole industry should benefit from a practical and convenient standard that saves library developers from having to re-invent the wheels of memory modeling.

This standard provides the basic infrastructue to write memory models in VHDL in terms of ways to define memory objects, procedures to perform various operations on memory such as read,write,initialization and memory corruption.

This presentation gives an overview of the memory standard and its current state of development. The various implementation strategies, global issues and glimpses of VITAL memory capabilities will also be discussed.The VITAL TAG is currently working on a detailed design of this standard and is planning to make it available to the industry in early next year.

Bio:
Ekambaram Balaji is working as a senior design engineer in the Design Tool Group at LSI Logic Corporation, CA, USA. Before joining LSI he served as a Member of the technical staff in the Simulation Modeling Group at Cadence Design Systems for more than five years, developing Verilog models for System and ASIC components. He has more than eight years of experience in the field of HDL Modeling for simulation. Ekambaram is currently responsible for the VITAL library development and Sign-Off methodology issues at LSI Logic. He is also a member of the VITAL Technical Action Group working towards extensions for VITAL'98.