1997 Abstracts and Bios by Track

ASIC/FPGA

• ASIC/FPGA Keynote:Change? . . . You ain't seen nothing yet! Jim Hively (abstract and bio)
• ASIC/FPGA Keynote:Exemplar Logic's Extreme Technology Overview Mike Bohm (abstract and bio)
• Exemplar Logic ASIC Synthesis Roadmap Michiel Ligthart (abstract and bio)
• Experiences Using Built-In Self Test Johan Starner, Joakim Adomat (abstract and bio)
• Inventra Intellectual Property Products Brian Barrera (abstract and bio)
• Memory modeling for 1998-1076.4 Vital Standard Ekambaram Balaji (abstract and bio)
• Synopsys & Mentor Graphics Design for Reuse Partnership--Reuse Methodology Manual Nick Ruddick, Mike Keating (abstract and bio)
• Using Leonardo for ASIC Design Shawn McCloud (abstract and bio)
• Using ModelSim for Mixed-HDL Design Valerie Rachko (abstract and bio)
• Standards in Digital Simulation Dennis Brophy (abstract and bio)

Design Environment

• A Custom Tool for Managing the Electronic Design Environment, M. Barry, D. Bishop, D. Colpoys, J. Vincent (abstract and bio)
• Capturing Cost and Metrics via the Web, Mark Ledebur (abstract and bio)
• Design Architect--Future Enhancements, Bruce Swanson (abstract and bio)
• Design Evolution: Completing the Configuration Management tool set, Rick Reid (abstract and bio)
• Design Evolution Concept, Managing Creativity Without Stifling It, Madhav Nerurkar (abstract and bio)
• EDA Uses of the WWW, Mark Noneman (abstract and bio)
• Exact Access Licensing Improvements, Mike Frison (abstract and bio)
• How to Date Stamp Gerber Artwork, Bruce Mayer (abstract and bio)
• Introduction to Perl: A Compliment to AMPLE, Michael Wallace (abstract and bio)
• Managing ICX Tools in a Board Station Environment, Kim Owen (abstract and bio)
• Licensing Panel / Q&A Forum, Scott Cate, John Wallick (abstract and bio)

Hardware/Software Co-Design

• A Software Environment for PCB Diagnosis, Elena Marchetti (abstract and bio)
• Development of Low-Power Microprocessor Family within Mentor Graphics, Vincent Rikkink (abstract and bio)
• A High-Performance Reconfigurable Coprocessor for Digital Signal Processing, G. Bois, B. Bosi, Y. Savaria (abstract and bio)

IC

• Automated Layout Generation Algorithm for Making CMOS-Compatible High-Voltage Transistors in a Digital Sub-Micron VLSI CMOS Process, Thomas VanEaton (abstract and bio)
• Calibre: From 0 to 5.1 Million in 6 Months, Pat LaCour (abstract and bio)
• Calibre Physical Verification for Deep Submicron, Roy Dunn (abstract and bio)
• Device Calculators Make Design Automation Simple, Michael Tedeschi (abstract and bio)
• Low-Power Design Environment for MOSIS, Dave Garrett, Mircea Stan (abstract and bio)
• Schematic Driven Layout Using the MOSIS Design Kit for Advanced Analog and Mixed-Signal Design, Abhimanyu Kolla, Mircea R. Stan (abstract and bio)
• Utilizing ICView in a Concurrent Engineering Environment, King Payne (abstract and bio)
• xCalibre Parasitic Extraction for Deep Submicron, Jon Gelsey (abstract and bio)

Library Data Management

• Library Keynote:The Library Time Machine, Kim Scott (abstract and bio)
• A Method to Use Personal VHDL Models With Library Components, Michael Pringle (abstract and bio)
• Parts SpeciaList, Mark Heidorn (abstract and bio)
• Using PDS for Library Development, George Ammon, Edward Mong (abstract and bio)
• Using the Web for Part Sharing, George Ammon, Antonio Barrera (abstract and bio)

PCB/MCM

• PCB Keynote: The designer of the twenty-first century - a commitment to excellence, Dieter Bergman (abstract and bio)
• A Method of Viewing DA Schematics Interactively, Gil Bellaiche (abstract and bio)
• Board Design Direction, Roger Rowe (abstract and bio)
• Chips-First HDI MCM Design Methods, Robert Marks (abstract and bio)
• Concurrent Board Layout Design, Janice Newhart, Raisa Wesenberg (abstract and bio)
• Concurrent Board Process using Viewpoints: Our Trials and Tribulations, Bill Bacher (abstract and bio)
• DFM - Design For Manufacturability, David Furst (abstract and bio)
• DFM, Really!, David Ransier, Mac Feezor (abstract and bio)
• Electrical Process Using MGC Variant Properties, Leo Dabbs (abstract and bio)
• Hierarchical System Design Reuse, Pete Klein (abstract and bio)
• History, Trends, and Future of Design and Manufacturing Verification Technology, Leigh Eichel (abstract and bio)
• Mechanical Data in an Electrical World - Present and Future, Kim Kimmel (abstract and bio)
• Parametric Trace Widths and Clearances, Greg Dance (abstract and bio)
• PCB Design Data Verification Using Scepter DFF, David Hall, Karen Kerns (abstract and bio)
• Practical Tips for Using RF Gateway to Transfer Layout Information from HP's Series IV into Mentor's Board Station, Dan Evers, Chris Swaim (abstract and bio)
• Using Geom Genie to Develop Re-Targetable Design for Manufacturing (DFM) Geometries, Liau Hon Chung (abstract and bio)
• Using WorkXpert to Resurface the Road to Concurrent Board Process, David Ransier, Mac Feezor (abstract and bio)
• Signal Integrity: The Design and Layout Revolution, Barry Heller (abstract and bio)

Simulation

• Adding VHDL Simulation Model to Existing Mentor Libraries Using a CDP-Based Netlister, Inna Lyusternik, Dan Weyer (abstract and bio)
• Application of ELDO HDL-A Simulation Environment to Micro-Machined Technology Modeling, M. Orlikowski, M. Zubert, W. Wojciak, A. Napieralski (abstract and bio)
• Creating IBIS Models for Interconnect Synthesis, Kim Owen (abstract and bio)
• HDL-A Versatility In Analog Modeling, Matthew Sprengeler (abstract and bio)
• Using Quicksim Assertions to compare WDB's to verify equivalency of a re-targeted ASIC, Hugh Blair (abstract and bio)

University

• A First Timer's View - VHDL to Layout in 9 Weeks, Roger Traylor (abstract and bio)
• A Two-Stage Adjusting All Digital Phase-Locked Loop, T. C. Bau, S. Mourad (abstract and bio)
• Optimizing Time Window through Hardware-Software Codesign in Undergraduate Projects, Roland Mercier (abstract and bio)
• The Role of a Concurrent Engineering Research & Development Group in Education and Industry, Milton Borsato (abstract and bio)
• Use of CAD Tools in the Integrated Computer Engineering Design (ICED) Curriculum, Augustus K. Uht (abstract and bio)
• Using Mentor Graphics' Hybrid Station in Teaching an Undergraduate Course in "Computer-Aided Designing of Electrical Components", Torsten Tuschick, Holger Riecke, Gert Winkler (abstract and bio)

Workflow/Process Improvement

• Application of Workflow Management Software for Design-Manufacturing Integration, H. M. Karandikar (abstract and bio)
• Common Process Deployment Using Workflow Management, Gil Alexander, Chris Withers (abstract and bio)
• Process Improvements Enabled by the RASSP Manufacturing Interface, Lynwood Hines (abstract and bio)
• Seamless CVE, A look at our first Year, Jim Kenney (abstract and bio)
• Using WorkXpert to Implement RASSP Electronic Design Workflows, Jeffrey Stavash (abstract and bio)
• Workflow: A New Paradigm for Critical Low Use Procedures, J. William Thompson (abstract and bio)
• Workflow Analysis and Design Environment (WADE), Perakath Benjamin (abstract and bio)
• WorkXpert Best Practices, Marty Fouch (abstract and bio)