Yesterday's methodologies are no longer adequate to meet today's high speed PCB design challenges. Engineers must now deal with many signal integrity and timing issues early in the design cycle to avoid costly and time consuming design - analyze - iterate processes.

These challenges are only met by a methodology that provides the engineer with tight coupling between the schematic and early signal integrity and timing analysis. In addition to analysis, the PCB must be designed and synthesized (routed to electrical constraints) to avoid iterations.

In addition, today's high speed designs are not single board designs, therefore the designer must consider all possible system variations and combinations. If only the motherboard is analyzed there is no guarantee that the system will function.

This paper presents a specific system design application comprised of a high speed multi-board system. It reviews the design methodology and tools used to solve the challenge of high-speed board-level synthesis, system-level analysis, and results correlation. It will illustrate unique aspects of system level design and analysis for high performance systems that make previous methodologies unsuitable and obsolete.

Bio:
Scott McMorrow currently works as a Signal Integrity Engineer for Stramond Corporation, a high speed digital design consulting firm serving the Pacific Northwest. Recently he has been lead design engineer on several Pentium Pro based PC server platforms for Intel, directing the design, signal integrity, and layout efforts on these systems using the Interconnectix tool set in a Mentor Graphics Board Station environment. A graduate of Virginia Polytechnic Institute with a BSEE, he has 16 years of real world experience designing high speed digital communications and computer systems.