A PCB Designer s "Exedrine moment" caused by explaining why an open or short occurred in a split plane is avoidable. The "paper tape" method of adding a void line to the power plane does not allow for connectivity checks until the board is built. Mentor Graphics has provided a method of defining and checking split power planes using power fills.

Starting with Librarian and ending with Fablink, this presentation will walk the PCB designer through the process of creating and checking split power planes. Error examples will demonstrate the check power fill function results. The presentation will include the steps necessary to analyze and correct reported problems.

Bio:
Karen McConnell is an electrical engineer for UNISYS Corporation. The UNISYS Computer Systems Group provides a range of powerful hardware and software technologies that serve as building blocks of advanced information management solutions. Besides designing high speed PCB boards, Karen develops processes (work around's) for using MGC Boardstation. She has 7 years experience using Mentor Graphics tools.