The Mentor Graphic GDT CAD tool has been applied to generate the layout/schematic of the NPN transistor in a BiCMOS process successfully. The technology file used to initiate the CAD tool is obtained by adding abstract material levels, contacts and geometry rules into the standard N-well 0.8 um CMOS technology file. The device generator is based on a low-cost BiCMOS process and is written in Lx and GENIE languages. In the Led window, this device generator is installed by a starting file. Therefore, the NPN transistorgenerated by this method can be called and the size can be changed just like standard N-channel and P-channel transistors. The same method can be applied togenerate a high performance BiCMOS process based on the twin-well CMOS technology. Any customized device (GPD-general purpose device) can be generatedby this method.

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