A generator-based standard cell library (GCMOS) has been developed using Mentor ICGEN. The library is compatible with all of the submicron CMOS processes offered through MOSIS. A methodology has been developed for using ICGEN which simplifies the user effort required to define a new cell for the library. A cell architecture file defines the transistor ordering and netlist; initial transistor sizes are defined via a sizing file. A manually generated routing core is used for connecting the transistors. ICGEN is used to size the transistors to user specifications, and add power rails, well plugs and additional wiring (if needed). The library is being used in a standard cell methodology that optimizes cell height versus time constraints for each separately placed/routed block within a design. The ICGen methodology and some preliminary results of the cell height optimization effort are presented.

Bio:
Bob Reese is an Associate Professor with the Electrical and Computer Engineering Department at Mississippi State University. He is also Director of the Microsystems Prototyping Lab associated with the MSU/NSF Engineering Research Center. His interests include VLSI CAD Frameworks and VLSI design methodologies.