Wire sizing has become an important and necessary step to optimize the performance of long interconnects in sub-micron ICs. Due to the limited ability of autorouters in handling complex variable wire width specifications, variable wire width assignment is usually done in a very ad hoc manner mainly by a tedious manual process.

This paper presents a post-layout wire sizing program that optimizes both the performance as well as the reliability of long interconnects for ICs designed using the GDT tools. The program, written in GENIE, first extracts the net to be optimized from the L layout database, then it iterates between electrical simulations (using SPICE) to determine the electromigration constraints and computing the wire sizes for performance and reliability optimization (using an optimum wire-sizing algorithm from Cong, et al.). Finally, the design is modified according to the wire-sizing results to produce the optimized layout.

Bio:
Kei-Yong Khoo is a senior development engineer in the Computer Science Department of the University of California, Los Angeles, and is pursuing his Ph.D. degree in the Electrical Engineering Department. From 1988 to 1990, he was a member of technical staff at Mentor Graphics in New Jersey, where he engaged in the