A Creative Class Project Based on VHDL, Synthesis and FPGA Design

C. G. Harrison, P. L. Jones
University of Manchester, England

The aim of this class project is to develop interpersonal and communication skills in a group working environment while at the same time providing experience in the planning and execution of a complex electronic design. The students are in the second year of an undergraduate program. The following criteria were taken into consideration when selecting the task to be undertaken.

  1. It must have immediate appeal for a young engineer.
  2. The design must be capable of being partitioned for group working.
  3. It must be challenging but achievable within the time available.
  4. There must be scope for individual assessment.

The redesign of the control electronics for a radio-controlled toy racing car has been found to satisfy all four of the criteria set for selection. The overall design is sufficiently complex to merit a group effort and it can be decomposed into several distinct partitions with clearly defined interfaces. The project teams comprise up to eight students. The students already have a strong background in design developed in their first year and are comfortable with the Mentor Graphics framework for logic simulation and VHDL. They have not, however, previously encountered AutoLogic or Xilinx FPGA design.

An initial exercise a walk-through has been written so students can take a simple design in VHDL through logic synthesis to an FPGA on a prototyping board to show that the configuration provides the expected functionality. Having the close integration of the Mentor and Xilinx tools gives rapid feedback on whether a VHDL defined behavior matches the realization in the car control hardware. Compared with previous experience of schematic capture using cell libraries, this combination of VHDL with synthesis and FPGA design has enabled relatively inexperienced student teams to work more productively and creatively and to achieve successful demonstrable results within a very demanding timescale.

Bio:
Dr Peter Jones is a senior lecturer in the Division of Electrical Engineering at the University of Manchester. For the past 10 years he has specialized in developing teaching methods in VLSI design training. Since 1992 his teaching interests have extended to include computer-based learning and he is now working with a team of eight universities developing courseware for the teaching of electronics design. His research has been in the field of high-performance bipolar circuit design and rapid prototyping. He has had over 50 journal publications on research and teaching.