CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20 percent of the total in well-designed circuits, and up to 80 percent of the total in circuits that have not been designed carefully. This current depends strongly on the relative sizes of the pull-up to pull-down paths. In this presentation we introduce the dynamic short-circuit ratio to model this parameter, which allows accurate estimation of currents, including the dynamic short-circuit current, and also results in improved delay estimation. Accuracy is typically within 10 percent of circuit-level simulation while operating at the switch-level of abstraction.

Bio:
Sanjay Dhar has been with Mentor Graphics since 1992. He is currently working on very high-performance algorithms for timing and power analysis. At Mentor Graphics, he has been working on the Lsim product including Lsim-DSM and Lsim Power Analyst. He is the inventor of the SPS (series-parallel switch) algorithm and holds an U.S. patent on this invention. He was employed at Bell Communication Research from 1987-1992 where he worked on switch-level and timing simulation algorithms, and on routing algorithms for communication networks. Sanjay Dhar holds the D.Sc and M.S degrees in Electrical Engineering from Washington University, St. Louis and the B.Tech degree from I.I.T, Kharagpur, India.