This panel session provides the opportunity to hear what new tools and features are available for ASIC and FPGA designers. The product areas of

Synthesis, Simulation, and Silicon Vendor Libraries will be discussed, looking forward from the B.2 release available in September this year, through 1997 and beyond.

Bio:
Steve Shively is the Silicon Systems Division's Manager of Silicon Vendor Operations (SVO) responsible for worldwide business and technical relatioships with ASIC and FPGA vendors. Steve has held various positions at Mentor Graphics, including LSI Logic and VLSI Technology Program Manager, Marketing Manager and Engineering Manager within SVO. Before joining Mentor Graphics, Steve was an Applications Engineering Manager with Tektronix responsible for contract software development and customer support hotline operations. Steve has also held various management positions at International Microcircuits, Inc. and was a design engineer and CAD engineer at Intel Corporation. Steve has a B.S.E.E. from Purdue University in West Lafayette, IN.

Cliff Lyons has been with Mentor Graphics since 1990. Currently, Cliff is the Product Line Manager for Synthesis and Static Timing. Prior to this position, he was Engineering Director for ATD, 2nd-level Engr. Mgr. for High-Level Synthesis, Test VHDL Simulation and Timing Analysis; project manager for CPF (Circuit PathFinder) 8.x, and a software engineer integrating the CPF software purchased from Performance CAD into the Falcon Framework. Before joining Mentor Graphics, Cliff was a General Partner for Mktg., Sales, Acctg. & Legal marketing manager for Performance CAD. Additionally, he held management positions at Advanced Micro Devices. Cliff has an MS in Electrical Engineering >from San Jose State University, an MBA & Juris Doctor (cum laude), Harvard Business School & Harvard Law School, and a BA in Chemistry (summa cum laude), Harvard College. In 1974, he was named a US Presidential Scholar.

Brian Caslis has nine years' experience in the EDA marketplace working with simulation products. Brian is currently Simulation Product Marketing Manager for Mentor Graphics' SSD division covering the QuickHDL products and QuickSim II. Before working in the EDA industry, Brian worked as a digital designer on board-level and ASIC projects for seven years. He holds a Bachelor's degree in Electrical Engineering from Worcester Polytechnic Institute.

Tom Feist is the AutoLogic FPGA Product Marketing Manager for Mentor Graphics. Tom has more than seven years' experience in EDA industry. He joined Mentor Graphics in 1989 and has served as a senior Field Application Engineer, Account Manager, Technical Marketing Engineer and Product Marketing Manager. Before joining Mentor Graphics, Feist was a design engineer for BBN Delta Graphics and Boeing Aerospace Company. Feist holds a BSEE degree from Washington State University.

Tom Hill is the Technical Marketing Engineer for AutoLogic II. Before joining Mentor Graphics, Tom worked for Allen-Bradley as a digital designer for three years. Prior to his employment at Allen-Bradley, he worked at Lockheed Sanders in Nashua, NH, for five years as a board, FPGA and ASIC Designer, where he learned VHDL as part of the F22 Fighter program. Tom also worked as an Applications Engineer for Mentor in Boston for three years supporting top-down ASIC design products including Simulation, Synthesis and Test. Tom graduated with BSEE Cleveland State University.